Objective 1:
Select appropriate PCB substrate and develop a reliable process for spin-coating highly planar polymer surfaces and fabricating low-loss single mode waveguides 

POLYNICES will develop for the first time a process for the spin-coating of PolyBoard material on a PCB substrate forming the basis for a EOPCB motherboard (from now on motherboard). The target PCB that will be selected must be rigid, have good dielectric properties to support high RF frequencies, good mechanical properties and its Coefficient of Thermal Expansion (CTE) must be compatible with the CTE (especially in the lateral direction) of the ZPU polymer that will be spin coated on it. Polyimide has excellent mechanical and dielectric properties -it is polymer based- thus with matching CTE, therefore it is identified as a first option. It can be ordered as a laminate on stiffeners, forming a rigid PCB for laying the optical polymer layers. Within POLYNICES, the PCB will be shaped to the size of a 4” wafer, to carry out the technology development. Fraunhofer’s lithography equipment can be scaled to 8” wafers, hence the potential scale up towards large-area PICs will be given with the existing consortium and infrastructure. Fraunhofer will develop the process for the spin-coating of highly planar surfaces on the selected PCB (target: <1 um deviation across wafer) independent of the topography of the surface, and then fabricate low-loss (target: < 0.5 dB/cm at 1550 nm, < 0.2 at 780 nm propagation loss) single mode waveguides. Appropriate lateral spot-size converters will be designed for lower coupling loss with the TriPleX™ chips (target: <0.2 dB per facet).

Objective 2:
Develop the process for accurate etching of recesses in the motherboard that will enable flip-chip integration and passive alignment of photonic chiplets, micro-optic elements and InP elements

POLYNICES will develop an etching process in the motherboard for the formation of recesses that will host the TriPleX™ chiplets, the non-linear crystals, the thin-film elements (TFEs), GRIN lenses and InP elements. The etching depth will be accurately controlled to not only allow the fabrication of vertical alignment stops on either two or all four sides of the pocket, that will enable the flip-chip integration and passive alignment of the TriPleX™ chiplets, but also the formation of appropriately sized pockets for the different micro-optical elements, resulting in straightforward assembly and good performance. The integration of micro-optical elements and free beam optics is a standard process in Fraunhofer’s PolyBoard toolbox and will be transferred to POLYNICES. The area in the recesses will be etched down to the copper layer of the PCB, revealing the traces and pads that the chiplets will land on. The same approach will be followed for the InP PDs, SOAs, Photoconductive antennas (all provided by Fraunhofer). The etching method will target small deviation of the etching depth of the vertical alignment stops (< 500 nm) accuracy. The developed method will result in small sidewall roughness, allowing low-loss (target: < 0.2 dB) coupling to the TriPleX™ chiplets and InP elements (target: < 0.5 dB).

Objective 3:
Develop multi-functional, flip-chip integration compatible Si3N4 PICs (chiplets), as photonic building blocks of highly scalable and low power consuming photonic integrated circuits

Photonic integrated circuits having the size of 1×1 cm2 will be fabricated in TriPleX™ as chiplets that will be inserted in the recesses formed in the motherboard. The chiplets will be based on LioniX’s existing external cavity and Blass matrix and first time squeezed light state generator designs, that will be modified to be compatible with flip-chip integration by having appropriate alignment stops, complementary to the polymer motherboard which will result in automatic alignment of the cores. The electrodes’ pads will be routed in grid array manner, instead at the edges. Their optical waveguides will be routed only on one side of the chiplet and will have spot size converters to ease coupling to the motherboard (< 0.2 dB per facet loss). Grating couplers on the chiplets will allow coupling to alignment loops. Actuation of the structures will be based on PZT stress-optic phase shifters. The high scalability of this approach is evident as it allows to use one chiplet design multiple times to achieve a larger, more complex photonic circuits. The novel chiplets to be developed are:

  • 8×8 Blass and Clements matrix chiplet (BM-8, CM-8) for THz beamforming and for Quantum Information Processing (QIP)
  • Low linewidth External Cavity Laser at 780 nm (ECL-780) and 1550 nm (ECL-1550)
  • 1:8 Squeezed light generator with integrated filters (SQ-8) for QIP

The C-band InP gain chips for the ECL chiplets will be provided by Fraunhofer, the 780 nm gain chips will be supplied by LioniX. It is noted that the targeted output power for the 780 nm external cavity laser is at least 100 mW and is demonstrated for the first time in TriPleX™.

Objective 4:
Development of compact, high speed and low driving voltage PZT stress optic actuators

POLYNICES will invest in PZT actuation for low power consumption and low heat dissipation at the PICs. An optimization strategy for the PZT stress-optic actuators will be followed, focusing on increasing the speed of the actuators (target: > 10 MHz), keeping the driving voltage required to achieve 2π phase shift < 40V, decreasing the electrode length (target: < 5 mm) and the power consumption (target: < 1 mW at 1kHz). The efforts will focus on two electrode configurations. Top-bottom electrodes provide more sensitivity and are promising for lowering the driving voltage to levels where commercial electronic driving solutions are very cheap. Top-top electrodes have higher breakdown voltage and can provide compact actuators (length < 5 mm). By optimizing the physical parameters of the electrodes, their position and distance above the waveguide, actuation speed > 10 MHz can be achieved. The PZTs that will be used for modulation will have an on-chip termination, and the transmission lines will be designed with matching impedance. The impedance value will be 1000 Ohm for lowering the driving power requirements of the PZTs.

Objective 5:
Develop single and arrayed versions of THz antenna elements (AE) with dielectric rods for high gain over a wide dynamic frequency range and low crosstalk 

POLYNICES will develop THz antennas on the EOPCB, that can be straightforwardly integrated with the InP elements, achieving in that way THz capabilities and unlocking a wide range of remote sensing applications. POLYNICES will bring a novel approach enabling to increase the radiation efficiency of broadband THz devices using Dielectric Rod Waveguide (DRW) technology. This technology provides a cost-affordable, low weight and compact alternative to electrically large lenses to efficiently radiate the power into a single beam. An array of DRW antennas can effectively combine the power of an arbitrarily large number of THz sources in a single output beam with low crosstalk. Contours will be formed on the EOPCB polymer to ease the alignment of the DRWs. Due to the DRW, it is still possible to place one element per AE in a dense configuration with good scanning properties. POLYNICES will leverage these advantages for realizing AE arrays operating over wide frequency range (> 1 THz), gain of 23.5 dBi, low cross-talk of < -20 dB with < 1 mm inter-element spacing. In that way the novel EOPCB platform will be suited for all kinds of applications where the light can stay on the platform, can be guided in the free-space, or can be transformed into THz signals and then radiated in the free-space.

Objective 6:
Develop a wafer scale process for low-loss flip-chip integration and investigate laser soldering of the Si3N4 chiplets into the EOPCB motherboard 

POLYNICES will develop a wafer scale process for flip-chipping the TriPleX™ chiplets into the recesses, aligning the waveguides and the electrode pads on the chiplet to the ones on the motherboard, and soldering the PIC in place. The integration process is facilitated by the clever design of the chiplets that have the optical waveguides with spot size converters on one side, and vertical alignment stops. The spot size converters will relax alignment tolerances and reduce coupling loss (target: < 0.2 dB per facet). The alignment process will be initially aided by active alignment through pairs of grating couplers on the chiplet that will allow reaching dedicated alignment loops on the motherboard. The passive process will be optimized to last < 30 s from picking up the chiplet to alignment in the pocket. Automated dispensing of solder material will be applied on the electrical pads of the motherboard which will be arranged in a grid array manner with approx. size ~100×100 μm2 before the flip-chipping of the chiplet by means of wafer level packaging services available in the market. POLYNICES will investigate laser soldering method that applies localized heat to melt the solder material without disturbing the optical alignment. The targeted speed will be < 1 min per chiplet. 

Objective 7:
Develop process for co-packaging of the electronic ICs with the motherboard, combine individual steps and consolidate a single process flow for the assembly and packaging of POLYNICES demonstrators 

The motherboard concept of POLYNICES enables the straightforward co-packaging of the electronic driving ICs with the optical subassembly, significantly reducing the packaging effort, as both interfaces lie on the same substrate, resulting in compact assemblies. The electronic design and fabrication of the PCB traces and pads connecting the electronic to the photonic components will be realized with standard processes before the spin-coating of the polymer material. The soldering of the electronic ICs will be realized after the soldering of the chiplets, as the unpopulated pads for the ICs will be used as test pads. The dispensing of the solder material on the pads for the electronic ICs will be carried out using existing wafer-level packaging services. Electronic components will be selected in appropriate compact packages or in bare dies that can be soldered to the back of the PCB board employing the soldering method with high throughput. The separately developed processes described in the previous objectives will be consolidated into a single, seamless fabrication and assembly flow that will be used for the packaging of POLYNICES demonstrators. The POLYNICES processes described have been carefully thought by the consortium considering the characteristics and tolerances of each material platform, to be perfectly compatible with each other.

Objective 8:
Develop the demonstrators of POLYNICES technology for FMCW THz spectrometer and Quantum Information Processing 

 POLYNICES will utilize the sophisticated assembly and packaging methodology, resulting from the consolidation of the processes to deliver two demonstrators that highlight the technology potential: 

  • Demo-1Optoelectronic THz FMCW spectrometer will be delivered in two versions A (precursor) and B (final). The final demo (Demo-1B) will integrate in the motherboard two ECL-1550 chiplets for optoelectronic self-heterodyne THz generation on high-speed InP-PDs, an BM-8 chiplet for THz beamforming (± 10o angle steering), high-gain arrayed THz antennas at the Tx and Rx paths, InP-PDs, SOAs for THz transmission, Photoconductive antennas for THz reception, TIAs and DRVs for signal amplification, a wavelength meter based on GRIN lenses and a free-space cavity. Demo-1A will be a precursor demonstrator that will not have beamforming functionality. 
  • Demo-2│Quantum Information Processors will also be delivered in two versions A (precursor) and B (final). Demo-2A will integrate in the motherboard four (4) CM-8 chiplets at the core of the processor to achieve a 16×16 matrix, thus scaling the processor without yield issues and without electrical pad density issues. It will have an integrated pump source consisting of an ECL-780, PPKTP non-linear crystals and filters for the generation of signal and idler entangled photon pairs. The output signals will be coupled by fiber array to external single photon detectors. Demo-2B will integrate nine (9) CM-8 chiplets to form a record size of 24×24 matrix. The pump source will generate an array of 8 squeezed light states from an ECL-1550 source combined with the SQ-8 chiplet that will feed the processor. External detectors will be used also in DEMO-2B. The back of the EOPCB will be populated with driver chips for the LD and the PZT elements. 

Control and driving electronics: Custom electronics will be developed for the driving of the PZT actuators, the control of the demonstrators and the readout of the signals. Appropriate microcontrollers, FPGAs and DACs will be used, and they will be developed. For the quantum processors the electronics will interface with the external commercial single photon detectors.

Objective 9:
System evaluation of POLYNICES demonstrators and validation of their performance in relevant settings

POLYNICES will develop the experimental setups and testing methodologies in order to evaluate the performance of the demonstrators within a functional system environment. The system testing will have two main objectives: 

  • First to validate the functionality of the demonstrators and thus the potential of POLYNICES technology for use in a wide variety of application domains. 
  • Second to assess the performance of the demonstrators compared to devices that are currently considered state of the art but rely on bulk and much more expensive components.
    In more detail: Demo-1 will be evaluated at quality control testing for plastics, in particular plastic pipes, focusing on resolution, penetration depth and defect identification. Demo-2 evaluation will focus on the ability of the processor to demonstrate Boson sampling, as well as the operation of quantum logic gates for the manipulation of high-dimensional quantum states, known as qubits. The quantum information processor although very forward looking, is expected to find application in many fields like quantum simulations for drug discovery (biomedicine).

Objective 10:
Consolidation of a commercialization strategy and definition of a Process Design Kit (PDK) that will lower the barrier for stakeholders to use POLYNICES technology

POLYNICES develops a powerful, highly scalable, and fully integrated platform, that provides all the functionalities that are still missing and are required today in the photonic industry. POLYNICES paves the way for a new technology of electronic-photonic integrated circuits (E-PICs) following the system in package paradigm by adding more functionality through integration (More-than-Moore). Furthermore, it will be very easy for designers to integrate them into their systems with excellent scalability, just like the co-packaged optics, but involving less integration steps. All the design rules and electronic-photonic building blocks of POLYNICES will form a process design kit (PDK) that will become available in the post-POLYNICES era. The PDK will be provided by Fraunhofer and LioniX, will be disseminated to the industry and stakeholders will be encouraged to evaluate its potential. POLYNICES will also follow a commercialization strategy for the demonstrators, which will consist of two key points: 

a) Market research that will review the target markets for each demonstrator and identify opportunities for fast commercialization like quality control in plastic manufacturing 
b) Manufacturability studies including cost analysis and scaling of the processes to high-volume production.